Figure 1 shows the basic architecture of the proposed EC++ model. It can be viewed as 4 discreet sections - the hardware on which EC++ code is to be run, communications libraries which deal with inter process communication on this hardware, the EC++/C++ relationship and the applications level.
When applications writes are developing code for an application, they may or may not be developing this code targeted at a particular hardware architecture. It is intended that the EC++ model will allow applications to be written in such a way as to allow targeting at specific hardware types (SIMD, MIMD etc) but the model itself should not imply any given architecture. Clearly then, it is logical that the applications libraries the top level of the model can be written independently of the design of EC++, as is normal within standard C++.
It is below the library level that we see the EC+++ model, its interaction with libraries and the interaction with inter process (inter base object) communication.